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operating temperature range * 0 c to +70 c0 c to +70 c0 c to +70 c 16-pin 16-pin 16-pin wide body plastic pin small outline small outline package package (soic) package (soic) ald500pc (16 bit) ald500sc (16 bit) ald500swc (16 bit) ald500apc (17 bit) ald500asc (17 bit) ALD500ASWC (17 bit) ald500aupc (18 bit) ald500ausc (18 bit) ald500auswc (18 bit) * contact factory for industrial temperature range benefits ? wide dynamic signal range ? very high noise immunity ? low cost, simple functionality ? automatic compensation and cancellation of error sources ? easy to use to acquire true 18 bit,17 bit, or 16 bit conversion and noise performance ? inherently linear and stable with temperature and component variations features ? resolution up to 18 bits with sign bit and over-range bit ? accuracy independent of input source impedances ? high input impedance of 10 12 w ? inherently filters and integrates any external noise spikes ? differential analog input ? wide bipolar analog input voltage range 3.5v ? automatic zero offset compensation ? low linearity error - as low as 0.002% ? fast zero-crossing comparator - 1 m s ? low power dissipation - 6mw typical ? automatic internal polarity detection ? low input current - 2pa typical ? microprocessor controlled conversion ? optional digital control from a microcon- troller, an asic, or a dedicated digital circuit ? flexible conversion speed versus resolution trade-off ald500au/ald500a/ald500 a dvanced l inear d evices, i nc. ordering information precision integrating analog processor applications ? true 4 1/2 digits to 5 1/2 digits plus sign measurements ? precision analog signal processor ? precision sensor interface ? high accuracy dc measurement functions ? portable battery operated instruments ? computer peripheral ? pcmcia general description the ald500au/ald500a/ald500 are integrating dual slope analog processors, designed to operate on 5v power supplies for building precision analog-to-digital converters. the ald500au/ald500a/ ald500 feature specifications suitable for 18 bit/17 bit/16 bit resolution conversion, respectively. together with three capacitors, one resistor, a precision voltage reference, and a digital controller, a precision analog to digital converter with auto zero can be implemented. the digital controller can be implemented by an external microcontroller, under either hardware (fixed logic) or software control. for ultra high resolution applications, up to 23 bit conversion can be implemented with an appropriate digital controller and software. the ald500 series of analog processors accept differential inputs and the external digital controller first counts the number of pulses at a fixed clock rate that a capacitor requires to integrate against an unknown analog input voltage, then counts the number of pulses required to deintegrate the capacitor against a known reference voltage. this unknown analog voltage can then be converted by the microcontroller to a digital word, which is translated into a high resolution number, representing an accurate reading. this reading, when ratioed against the reference voltage, yields an accurate, absolute voltage measurement reading. the ald500 analog processors consist of on-chip digital control circuitry to accept control inputs, integrating buffer amplifiers, analog switches, and voltage comparators. it functions in four operating modes, or phases, namely auto zero, integrate, deintegrate, and integrator zero phases. at the end of a conversion, the comparator output goes from high to low when the integrator crosses zero during deintegration. ald500 analog processors also provide direct logic interface to cmos logic families. ? 1999 advanced linear devices, inc. 415 tasman drive, sunnyvale, california 94089 -1706 tel: (408) 747-1155 fax: (408) 747-1286 http://www.aldinc.com pin configuration v dd 1 2 3 14 15 16 4 13 b 5 12 a v + ref 6 7 8 10 11 v ss c az c int b uf agnd v - ref c + ref 9 v - in v + in c out dgnd pc, sc, swc package c - ref ald500
1-2 advanced linear devices ald500au/ald500a/ald500 general theory of operation dual-slope conversion principles of operation the basic principle of dual-slope integrating analog to digital converter is simple and straightforward. a capacitor, c int , is charged with the integrator from a starting voltage, v x , for a fixed period of time at a rate determined by the value of an unknown input voltage, which is the subject of measurement. then the capacitor is discharged at a fixed rate, based on an external reference voltage, back to v x where the discharge time, or deintegration time, is measured precisely. both the integration time and deintegration time are measured by a digital counter controlled by a crystal oscillator. it can be demonstrated that the unknown input voltage is determined by the ratio of the deintegration time and integration time, and is directly proportional to the magnitude of the external reference voltage. the major advantages of a dual-slope converter are: a. accuracy is not dependent on absolute values of integration time t int and deintegration time t dint , but is dependent on their relative ratios. long-term clock frequency variations will not affect the accuracy. a standard crystal controlled clock running digital counters is adequate to generate very high accuracies. b. accuracy is not dependent on the absolute values of r int and c int . as long as the component values do not vary through a conversion cycle, which typically lasts less than 1 second. c. offset voltage values of the analog components, such as v x , are cancelled out and do not affect accuracy. d. accuracy of the system depends mainly on the accuracy and the stability of the voltage reference value. e. very high resolution, high accuracy measurements can be achieved simply and at very low cost. an inherent benefit of the dual slope converter system is noise immunity. the input noise spikes are integrated (averaged to near zero) during the integration periods. integrating adcs are immune to the large conversion errors that plague successive approximation converters and other high resolution converters and perform very well in high-noise environments. the slow conversion speed of the integrating converter provides inherent noise rejection with at least a 20db/decade attenuation rate. interference signals with frequencies at integral multiples of the integration period are, theoretically, completely removed. integrating converters often establish the integration period to reject 50/60hz line frequency interference signals. the relationship of the integrate and deintegrate (charge and discharge) of the integrating capacitor values are shown below: v int = v x - (v in . t int / r int . c int ) figure 1. ald 500 functional block diagram sw - r - + - + + - + - (1) (14) (15) c out dgnd level shift polarity detection phase decoding logic comp2 comp1 integrator buffer analog switch control signals control logic a b agnd (10) (5) (11) (7) (9) (8) (6) (4) (2) (16) (13) (12) v dd v ss c int c int r int c az c az c - ref sw az sw s sw r sw r c ref sw az sw in sw g sw in c + ref v + ref v - ref sw - r sw + r sw + r v - in v + in buf (3)
ald500au/ald500a/ald500 advanced linear devices 1-3 (integrate cycle) (1) v x = v int - (v ref . t dint / r int . c int ) (deintegrate cycle) (2) combining equations 1 and 2 results in: v in / v ref = -t dint / t int (3) where: v x = an offset voltage used as starting voltage v int = voltage change across c int during t int and during t dint (equal in magnitude) v in = average, or an integrated, value of input voltage to be measured during t int (constant v in ) t int = fixed time period over which unknown voltage is integrated t dint = unknown time period over which a known reference voltage is integrated v ref = reference voltage c int = integrating capacitor value r int = integrating resistor value actual data conversion is accomplished in two phases: input signal integration phase and reference voltage deintegration phase. the integrator output is initialized to 0v prior to the start of input signal integration phase. during input signal integration phase, internal analog switches connect v in to the buffer input where it is maintained for a fixed integration time period (t int ). this fixed integration period is generally determined by a digital counter controlled by a crystal oscillator. the application of v in causes the integrator output to depart 0v at a rate determined by v in and a direction determined by the polarity of v in . the reference voltage deintegration phase is initiated immediately after t int , within 1 clock cycle. during reference voltage deintegration phase, internal analog switches connect a reference voltage having a polarity opposite that of v in to the integrator input. simultaneously the same digital counter controlled by the same crystal oscillator used above is used to start counting clock pulses. the reference voltage deintegration phase is maintained until the comparator output inside the dual slope analog processor changes state, indicating the integrator has returned to 0v. at that point the digital counter is stopped. the deintegration time period (t dint ), as measured by the digital counter, is directly proportional to the magnitude of the applied input voltage. after the digital counter value has been read, the digital counter, the integrator, and the auto zero capacitor are all reset to zero through an integrator zero phase and an auto zero phase so that the next conversion can begin again. in practice, this process is usually automated so that analog-to- digital conversion is continuously updated. the digital control is handled by a microprocessor or a dedicated logic controller. the output, in the form of a binary serial word, is read by a microprocessor or a display adapter when desired. figure 2. basic dual-slope converter s1 c int v int r int switch driver control logic polarity control ref switches integrator comparator phase control analog input (v in ) output integrator v in v full scale v in 1/2 v full scale t int t dint v int = 4.1v max ab figure 2. basic dual-slope converter + + - voltage reference c out polarity detection - t dint v x 0 microcontroller (control logic + counter)
1-4 advanced linear devices ald500au/ald500a/ald500 operating electrical characteristics t a = 25 c v dd = +5v v ss = -5v unless otherwise specified; c az = c ref = 0.47 m f 500au 500a 500 parameter symbol min typ max min typ max min typ max unit test conditions resolution 15 30 30 60 60 m v note 1 zero-scale z se 0.0025 0.003 0.005 % error 0.003 0.005 0.008 % 0 c to 70 c end point e nl 0.005 0.005 0.010 0.005 0.015 % notes 1, 2 linearity 0.007 0.015 0.020 0 c to +70 c best case n l 0.0025 0.003 0.005 0.003 0.008 % notes 1, 2 straight line linearity 0.004 0.008 0.015 0 c to +70 c zero-scale tc zs 0.3 0.6 0.3 0.7 0.3 0.7 m v/ c0 c to +70 c temperature coefficient 0.15 0.3 0.15 0.35 0.15 0.35 ppm/ c note 1 full-scale s ye 0.005 0.008 0.01 % symmetry error (rollover error) 0.008 0.010 0.012 % 0 c to 70 c full-scale tc fs 1.3 1.3 1.3 ppm/ c0 c to +70 c temperature coefficient input i in 222pav in = 0v current common-mode cmvr v ss +1.5 v dd -1.5 v ss +1.5 v dd -1.5 v ss +1.5 v dd -1.5 v voltage range integrator v int v ss +0.9 v dd -0.9 v ss +0.9 v dd -0.9 v ss +0.9 v dd -0.9 v output swing analog input v in v ss +1.5 v dd -1.5 v ss +1.5 v dd -1.5 v ss +1.5 v dd -1.5 v agnd = 0v signal range voltage v ref v ss +1 v dd -1 v ss +1 v dd -1 v ss + 1 v dd -1 v reference range absolute maximum ratings supply voltage, v + 13.2v differential input voltage range -0.3v to v + +0.3v power dissipation 600 mw operating temperature range pc, sc, swc package 0 c to +70 c storage temperature range -65 c to +150 c lead temperature, 10 seconds +260 c
ald500au/ald500a/ald500 advanced linear devices 1-5 dc electrical characteristics t a = 25 c v + = 5.0v unless otherwise specified;c az = c ref = 0.47 m f 500au 500a 500 parameter symbol min typ max min typ max min typ max unit test conditions supply current i s 0.6 1.0 0.6 1.0 0.6 1.0 ma v s = 5v , a =1,b=1 power dissipation p d 10 10 10 mw v s = 5v positive supply range v +s 4.5 5.5 4.5 5.5 4.5 5.5 v note negative supply range v -s -4.5 -5.5 -4.5 -5.5 -4.5 -5.5 v note 4 comparator logic 1, v oh 44 4vi source = 400 m a output high comparator logic 0, v ol 0.4 0.4 0.4 v i sink = 1.1ma output low logic 1, input high v ih 3.5 3.5 3.5 v voltage logic 0, input low v il 11 1v voltage logic input current i l 0.01 0.01 0.01 m a comparator delay t d 111 m sec note 5 notes: 1. integrate time 3 66 msec., auto zero time 3 66 msec., v int = 4v, v in = 2.0v full scale resolution = v int /integrate time/clock period 2. end point linearity at 1/4, 1/2, 3/4 full scale after full scale adjustment. 3. rollover error also depends on c int , c ref , c az characteristics. 4. contact factory for other power supply operating voltage ranges, including vsupply = 3v or vsupply = 2.5v. 5. recommended selection of clock periods of one of the following: t clk = 0.27 m sec, 0.54 m sec, or 1.09 m sec which corresponds to clock frequencies of 3.6864 mhz, 1.8432 mhz, 0.9216 mhz respectively. ~ figure 3. ald500 timing diagram ~ ~ ~ ~ ~ ~ 66.667 msec. 123,093 clock pulses positive input signal negative input signal ~ ~ 66.667 msec. 0.5416 s 123,093 clock pulses ~ ~ ~ ~ c out b input a input 1.8432 mhz clock 1 conversion cycle auto zero phase input signal integration phase reference voltage deintegration phase integrator zero phase auto zero phase fixed number of clock pulses by design. variable number of clock pulses. ~ clock data in or clock data out of counters within the the microcontroller or fixed logic controller, as needed. fixed period of approx.1 msec. at v in max, max. number of clock pulses = 246,185 not valid stop counter upon detection of comparator output going from high to low state. start deintegration cycle start integration cycle start conversion cycle ~ ~ ~ ~ ~ ~ start integrator zero cycle c out not valid repeat conversion cycle
1-6 advanced linear devices ald500au/ald500a/ald500 1c int integrator capacitor connection. 2v ss negative power supply. 3c az the auto-zero capacitor connection. 4 buf the integrator resistor buffer connection. 5 agnd this pin is analog ground. 6c - ref negative reference capacitor connection. 7c + ref positive reference capacitor connection. 8v - ref external voltage reference (-) connection. 9v + ref external voltage reference (+) connection. 10 v - in negative analog input. 11 v + in positive analog input. 12 a converter phase control msb input. 13 b converter phase control lsb input. 14 c out comparator output. c out is high during the integration phase when a positive input voltage is being integrated and is low when a negative input voltage is being integrated. a high-to-low transition on c out signals the processor that the deintegrate phase is completed. c out is undefined during the auto-zero phase. it should be monitored to time the integrator zero phase. 15 dgnd digital ground. 16 v dd positive power supply. pin description pin no. symbol description switch functions input reference input auto zero reference v in =agnd system connect polarity sample offset conversion control phase logic sw in sw + r or sw - r sw az sw r sw g sw s auto zero a = 0, b = 1 open open closed closed closed open input signal a = 1, b = 0 closed open open open open open integration reference voltage a = 1, b = 1 open closed* open open closed open deintegration integrator a = 0, b = 0 open open open closed closed closed output zero *sw + r would be closed for a positive input signal. sw - r would be closed for a negative input signal. table 1. conversion phase and control logic internal analog switch functions
ald500au/ald500a/ald500 advanced linear devices 1-7 ald500au/ald500a/ald500 conversion cycle the ald500au/ald500a/ald500 conversion cycle takes place in four distinct phases, the auto zero phase, the input signal integration phase, the reference voltage deintegration phase, and the integrator zero phase. a typical measurement cycle uses all four phases in an order sequence as mentioned above. the internal analog switch status for each of these phases is summarized in table 1. the following is a detailed description of each one of the four phases of the conversion cycle. auto zero phase (az phase) the analog-to-digital conversion cycle begins with the auto zero phase, when the digital controller applies low logic level to input a and high logic level to input b of the analog processor. during this phase, the reference voltage is stored on reference capacitor c ref , comparator offset voltage and the sum of the buffer and integrator offset voltages are stored on auto zero capacitor c az . during the auto zero phase, the comparator output is characterized by an indeterminate waveform. during the auto zero phase, the external input signal is disconnected from the internal circuitry of the ald500au/ ald500a/ald500 by opening the two sw in analog switches and connecting the internal input nodes internally to analog ground. a feedback loop, closed around the integrator and comparator, charges the c az capacitor with a voltage to compensate for buffer amplifier, integrator and comparator offset voltages. this is the system initialization phase, when a conversion is ready to be initiated at system turn-on. in practice the converter can be operated in continuous conversion mode, where az phase must be long enough for the circuit conditions to settle out any system errors. typically this phase is set to be equal to t int . input signal integration phase (int phase) during the input signal integration phase (int), the ald500au/ ald500a/ald500 integrates the differential voltage across the (v + in ) and (v - in ) inputs. the differential voltage must be within the device's common-mode voltage range cmvr. the integrator charges c int for a fixed period of time, or counts a fixed number of clock pulses, at a rate determined by the magnitude of the input voltage. during this phase, the analog inputs see only the high impedance of the noninverting operational amplifier input of the buffer. the integrator responds only to the voltage difference between the analog input terminals, thus providing true differential analog inputs. the input signal polarity is determined by software control at the end of this phase: c out = 1 for positive input polarity; c out = 0 for negative input polarity. the value is, in effect, the sign bit for the overall conversion result. the duration of this phase is selected by design to be a fixed time and depends on system parameters and component value selections. the total number of clock pulses or clock counts, during integration phase determine the resolution of the conversion. for high resolution applications, this total number of clock pulses should be maximized. the basic unit of resolution is in m v/count. before the end of this phase, comparator output is sampled by the microcontroller. this phase is terminated by changing logic inputs ab from 10 to 11. reference voltage deintegration phase ( d int phase) at the end of the input signal integration phase, reference voltage deintegration phase begins. the previously charged reference capacitor is connected with the proper polarity to ramp the integrator output back to zero. the ald500au/ ald500a/ald500 analog processors automatically selects the proper logic state to cause the integrator to ramp back toward zero at a rate proportional to the reference voltage stored on the reference capacitor. the time required to return to zero is measured by the counter in the digital processor using the same crystal oscillator. the phase is terminated by the comparator output after the comparator senses when the integrator output crosses zero. the counter contents are then transferred to the register. the resulting time measurement is proportional to the magnitude of the applied input voltage. the duration of this phase is precisely measured from the transition of ab from 10 to 11 to the falling edge of the comparator output, usually with a crystal controlled digital counter chain. the comparator delay contributes some error in this phase. the typical comparator delay is 1 m sec . the comparator delay and overshoot will result in error timing, which translates into error voltages. this error can be zeroed and minimized during integrator output zero phase and corrected in software, to within 1 count of the crystal clock (which is equivalent to within 1 lsb, when 1 clock pulse = 1 lsb). integrator zero phase ( i ntz phase) this phase guarantees the integrator output is at 0v when the auto zero phase is entered, and that only system offset voltages are compensated. this phase is used at the end of the reference voltage deintegration and is used for applications with high resolutions. if this phase is not used, the value of the auto-zero capacitor (c az ) must be much greater than the value of the integration capacitor (c int ) to reduce the effects of charge-sharing. the integrator zero phase should be programmed to operate until the output of the comparator returns "high". a typical integrator zero phase lasts 1msec. the comparator delay and the controller's response latency may result in overshoot causing charge buildup on the integrator at the end of a conversion. this charge must be removed or performance will degrade. the integrator output zero phase should be activated (ab = 00) until c out goes high. at this point, the integrator output is near zero. auto zero phase should be entered (ab = 01) and the ald500au/ ald500a/ald500 is held in this state until the next conversion cycle.
1-8 advanced linear devices ald500au/ald500a/ald500 differential inputs (v + in ,v - in) the ald500au/ald500a/ald500 operates with differential voltages within the input amplifier common-mode voltage range. the amplifier common-mode range extends from 1.5v below positive supply to 1.5v above negative supply. within this common-mode voltage range, common-mode rejection is typically 95db. the integrator output also follows the common-mode voltage. when large common-mode voltages with near full-scale differential input voltages are applied, the input signal drives the integrator output to near the supply rails where the integrator output is near saturation. under such conditions, linearity of the converter may be adversely affected as the integrator swing can be reduced. the integrator output must not be allowed to saturate. typically, the integrator output can swing to within 0.9v of either supply rails without loss of linearity. analog ground analog ground is v - in during auto zero phase and reference voltage deintegration phase. if v - in is different from analog ground, a common-mode voltage exists at the inputs. this common mode signal is rejected by the high common mode rejection ratio of the converter. in most applications, v - in is set at a fixed known voltage (i.e., power supply ground). all other ground connections should be connected to digital ground in order to minimize noise at the inputs. differential reference (v + ref , v - ref ) the reference voltage can be anywhere from 1v of the power supply voltage rails of the converter. roll-over error is caused by the reference capacitor losing or gaining charge due to the stray capacitance on its nodes. the difference in reference for (+) or (-) input voltages will cause a roll-over error. this error can be minimized by using a large reference capacitor in comparison to the stray capacitance. phase control inputs (a, b) the a and b logic inputs select the ald500au/ald500a/ ald500 operating phase. the a and b inputs are normally driven by a microprocessor i/o port or external logic, using cmos logic levels. for logic control functions of a and b logic inputs, see table 1. comparator output (c out ) by monitoring the comparator output during the input signal integration phase, which is a fixed signal integrate time period, the input signal polarity can be determined by the microcontroller controlling the conversion. the comparator output is high for positive signals and low for negative signals during the input signal integration phase. the state of the comparator should be checked by the microcontroller at the end of the input signal integration phase, just before transition to the reference voltage deintegration phase. for very low level input signals noise may cause the comparator output state to toggle between positive and negative states. for the ald500au/ald500a/ald500, this noise has been minimized to typically within one count. at the start of the reference voltage deintegration phase, comparator output is set to high state. during the reference voltage deintegration phase, the microcontroller must monitor the comparator output to make a high-to-low transition as the integrator output ramp crosses zero relative to analog ground. this transition indicates that the conversion is complete. the microcontroller then stops and records the pulse count. the internal comparator delay is 1 m sec, typically. the comparator output is undefined during the auto zero phase. figure 4. comparator output analog input integrate reference deintegrate zero crossing comparator output (c out ) reference deintegrate zero crossing integrator output (v int ) analog input integrate integrator output (v int ) negative input signal (v in ) positive input signal (v in ) external input polarity detection comparator output (c out ) 0v external input polarity detection
ald500au/ald500a/ald500 advanced linear devices 1-9 applications and design notes determination and selection of system variables the procedure outlined below allows the user to determine the values for the following ald500au/ald500a/ald500 system design variables: (1) determine input voltage range (2) clock frequency and resolution selection (3) input integration phase timing (4) integrator timing components (r int , c int ) (5) auto zero and reference capacitors (6) voltage reference system timing figure 3 and figure 4 show the overall timing for a typical system in which ald500au/ald500a/ald500 is interfaced to a microcontroller. the microcontroller drives the a, b inputs with i/o lines and monitors the comparator output, c out , using an i/o line or dedicated timer-capture control pin. it may be necessary to monitor the state of the comparator output in addition to having it control a timer directly during the reference deintegration phase. there are four critical timing events: sampling the input polarity; capturing the deintegration time; minimizing overshoot and properly executing the integrator output zero phase. selecting input integration time for maximum 50/60 cycle noise rejection, input integration time must be picked as a multiple of the period of line frequency. for example, t int times of 33msec, 66msec and 100 msec maximize 60hz line rejection, and 20msec, 40 msec, 80msec, and 100 msec maximize 50hz line rejection. note that t int of 100 msec maximizes both 60 hz and 50hz line rejection. int and d int phase timing the duration of the reference deintegrate phase (d int) is a function of the amount of voltage charge stored on the integrator capacitor during int phase, and the value of v ref . the d int phase must be initiated immediately following int phase and terminated when an integrator output zero-crossing is detected. in general, the maximum number of counts chosen for d int phase is twice to three times that of int phase with v ref chosen as a maximum voltage relative to v in . for example, v ref = v in (max)/2 would be a good reference voltage. integrating resistor (r int ) the desired full-scale input voltage and amplifier output current capability determine the value of r int . the buffer and integrator amplifiers each have a full-scale current of 20 m a. the value of r int is therefore directly calculated as follows: r int =v in max / 20 m a where: v in max = maximum input voltage desired (full count voltage) r int = integrating resistor value for minimum noise and maximum linearity, r int should be in the range of between 50k w to 150k w . integrating capacitor (c int ) the integrating capacitor should be selected to maximize integrator output voltage swing v int , for a given integration time, without output level saturation. for +/-5v supplies, recommended v int range is between +/- 3 volt to +/-4 volt. using the 20 m a buffer maximum output current, the value of the integrating capacitor is calculated as follows: c int = (t int ) . (20 x 10 -6 ) / v int where: t int = input integration phase period v int = maximum integrator output voltage swing it is critical that the integrating capacitor must have a very low dielectric absorption, as charge loss or gain during conversion directly converts into an error voltage. polypropylene capacitors are recommended while polyester and polybicarbonate capacitors may also be used in less critical applications. reference (c ref ) and auto zero (c az ) capacitors c ref and c az must be low leakage capacitors (e.g. polypropylene types). the slower the conversion rate, the larger the value c ref must be. recommended capacitor values for c ref and c az are equal to c int . larger values for c az and c ref may also be used to limit roll-over errors. calculate v ref the reference deintegration voltage is calculated using: v ref = (v int ) . (c int ) . (r int ) / 2(t int ) converter noise the converter noise is the total algebraic sum of the integrator noise and the comparator noise. this value is typically 14 m v peak to peak. the higher the value of the reference voltage, the lower the converter noise. such sources of noise errors can be reduced by increased integration times, which effectively filter out any such noise. if the integration time periods are selected as multiples of 50/60hz frequencies, then 50/60hz noise is also rejected, or averaged out. the signal-to-noise ratio is related to the integration time (t int ) and the integration time constant (r int ) (c int ) as follows: s/n (db) = 20 log ((v int / 14 x 10 -6 ) . t int /(r int . c int )) this converter noise can also be reduced by using multiple samples and mathematically averaged. for example, taking 16 samples and averaging the readings result in a mathematical (by software) filtering of noise to less than 4 m v.
1-10 advanced linear devices ald500au/ald500a/ald500 equations and derivations dual slope analog processor equations and derivations are as follows: 1 60hz 2.0 20x10 -6 = ~ = ~ = ~ design examples we now apply these equations in the following design examples. design example 1: 1. pick resolution = 16 bit. 2. pick t int = 4x = 4 x 16.6667 msec. 3. pick clock period = 1.08507 s and number of counts 4. pick v in max value, e.g., v in max = 2.0 v i b max = 20 a r int = = 100 k 5. applying equation (3) to calculate c int: 6. pick c ref and c az 3 c int : c ref c az 0.33 f 7. pick t dint = 2 x t int = 133.3334 msec 8. calculate v ref v int max . c int . r int t dint max = = = 4 x 0.33 x 10 -6 x 100 x 10 3 133.3334 x 10 -3 0.99v 1.00v = 0.0666667 sec. v v 1 r int . c int v in (t)dt = 0 t int t dint v in = v ref . t int 1 t int . v in = v ref . t dint (2a) (2) (1) c int = v int t int . i b (3) r int = v in max i b max (4) for v in (t) = v in (constant): from equation (2a), or rearranging equations (3) and (4): at v int = v int max, equation (6) becomes: combining (6a) and (7): in equation (5b), substituting equation (8) for t int : for t dint max = 2 x t int , equation (9) becomes: v in max . t int t dint max v in . t int t dint (5a) (5b) t int = c int . v int i b (6) i b max = v in max r int (7) v ref = v ref = . . . t int = c int . v int max . r int v in max (8) v in max . t dint max v ref = c int . v int max . r int v in max = c int . v int max . r int t dint max (9) v ref = c int . v int max . r int 2t int (10) r int . c int r int . c int v ref . t dint r int . c int . . . t int = c int . v int max i b max and at v in max, the current i b is also at a maximum level, for a given r int value: v in i b = (6a) c int = (0.0666667)(20x10 -6 )/4 where v int = 4.0v 0.33 f design example 2: 1. select resolution of 17 bit. total number of counts during t int is131,072. 2. we can pick t int of 16.6667 msec. x 5 = 83.3333 msec. or alternately, pick t int equal 16.6667 msec. x 6 = 100.00 msec. (for 60 hz rejection) which is t int = 20.00 msec. x 5 therefore, using t int = 100 msec. would achieve both 50 hz and 60 hz cycle noise rejection. for this example, the following calculations would assume t int of 100 msec. now select period equal to 0.5425 sec. (clock frequency of 1.8432 mhz) = 66.6667ms = ~ = 100.00 msec. (for 50 hz rejection) 0.0666667 1.08507x10 -6 over t int = = 61440
ald500au/ald500a/ald500 advanced linear devices 1-11 3. pick v in max = 2v for i b max = 20 a, applying equation (4), 4. calculate, using equation (3) for c int : use c int 0.47 f as the closest practical value. 5. pick c ref and c az = 0.47 f 6. pick t dint = 2 x t int = 200 msec. 7. calculate the value for v ref , from equation (10): v ref = 2 20x10 -6 = 0.83 f 2 20x10 -6 = 0.5 f c int . v int max . r int t dint max = 1.00v = 0.1666667 sec. 0.5 x 10 -6 x 4 x 100 x 10 3 200 x 10 -3 ~ design example 3: 1. pick resolution of 18 bit. total number of counts during t int is 262,144. 2. pick t int = 16.66667 msec. x 10 cycles this t int allows clock period of 0.5425 sec. and still achieve 18 bits resolution. 3. again, as shown from previous example, pick v in max = 2v for i b max = 20 a, r int = = 100 k 4. next, we calculate c int: c int = (0.1666667) x (20 x 10 -6 )/4 in this case, use cint = 1.0 f to keep v int < 4.0v 5. pick c ref and c az = 1.0 f 6. select t dint = 2 x t int = 333.333 msec. 7. calculate v ref as shown in the previous examples and v ref = 1.00v 4 245776 or 16.276 v/count 16.276 x v int max v in max = 8.138 v/count 20 x 10 -6 2 = 100 k design example 4: objective: 5 1/2 digit + sign +over-range measurement. 1. pick t int = 133.333 msec. for 60hz noise rejection. (16.6667 msec. x 8 cycles) frequency = 1.8432 mhz clock period = 0.5425 sec. during input integrate phase, for v int = 4.0v, the basic resolution is for v in max = 2.00v, the input resolution is 2. pick v in range = 2v for i b = 20 a, r int = 3. calculate c int = (0.133333) x (20 x 10 -6 )/4 = 0.67 f 4. pick c ref = c az = 0.67 f 5. select t dint = 2 x t int = 266.667 msec. 6. calculate v ref as shown in design example 1, substituting the appropriate values: c int . v int max . r int t dint max v ref = ~ = 1.005v r int = = 100 k c int = (0.1) x (20 x 10 -6 /4) ~ ~ 133.333 x 10 -3 0.5425 x 10 -6 = (assume v int max = 4v) (v int max = 4.0v) total count = = 245776

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